The present invention relates to a semiconductor device having a multi-bit data input/output terminal (hereinafter referred to as "data I/O terminal"). The present invention also relates to a method and apparatus for testing and inspecting the semiconductor device by dividing the memory of the semiconductor device into a number of memory blocks and executing a test by use of a conventional testing circuit which outputs test data of a limited number of bits corresponding to the number of bits of the data I/O terminal of each memory block.
In recent years, more and more CPUs capable of processing data of a larger number of bits have been developed, and more and more higher-speed peripheral computer devices have been developed. In accordance with this trend, the main memory of a computer and the memories of its peripheral devices are also required to operate at high speed without consuming high power. They are also required to operate at high frequency and process data of a large number of bits.
In order to evaluate the function of a memory employed in a system, a performance evaluating standard generally referred to as Fill Frequencies is proposed and widely used as guidelines for product development and system development. To satisfy the values prescribed in the Fill Frequencies and enable data transfer of a few gigabytes per second, for example, it is demanded that the number of bits of data I/O terminals be increased. For example, 32-bit data I/O terminals are required in the case of a 64M-DRAM, and 64- to 128-bit data I/O terminals are required in the case of a 1G-DRAM.
With an increase in the storage capacity of a memory, a longer time is needed to test a semiconductor device. In an effort to shorten the test time, two methods are available at present. In one of the methods, a test device itself is incorporated in a semiconductor device. In the other methods, a simultaneous measurement system is adopted which tests a number of semiconductor devices at one time.
An MBT (multi-bit test) method is known as the former method. This method tests a semiconductor device by checking whether or not the bit configuration of data to be examined coincides with that of test data.
In the simultaneous measurement system, the time actually required for testing one semiconductor device is shortened by increasing the number of semiconductor devices placed in one test station for simultaneous measurement or by increasing the number of test stations provided for the test system (e.g., from two stations to four stations).
In order to test a product having a larger number of data I/O terminals, it may be possible to increase the number of data pins provided for a test station. However, this method necessitates investment in plant and equipment, increasing the cost for test. In addition, if a larger number of data I/O terminals are provided, the number of devices that can be simultaneously measured in one station is inevitably small.
Under the above circumstances, there is a demand for improved test devices.
Many of existing semiconductor devices have 8-bit or 16-bit data I/O terminals. The testing apparatuses owned by manufacturers are designed to correspond to such a number of bits, and can simultaneously test a large number of devices whose data I/O terminals correspond to the number of bits.
If the data I/O terminals of semiconductor devices provided from now on comprise an increased number of bits, it will be necessary to increase the number of data pins provided for one test station. To be more specific, a new data I/O driver has to be added to the testing apparatus of an existing simultaneous measurement system, and a computer circuit has to be additionally provided. This cannot be done without incurring high expenses for investment in plant and equipment.
On the other hand, the MBT method has problems in that test data is not necessarily reliable. To be more specific, the unit number of bits (i.e., the number of bits which can be processed at one time) increases in accordance with an increase in the storage capacity of a memory. That is, the unit number of bits is "16" in the case of a 16M-DRAM, "32" in the case of a 64M-DRAM, "64" in the case of a 256M-DRAM, and "128" in the case of a 1G-DRAM. If the unit number of bits increases in this manner, the test data may not be necessarily reliable due to cell interference, bit line interference, or the like. In addition, if a redundancy circuit is used in place of a defective address, data check has to be executed again bit by bit.
Moreover, the ratio of the area of the test device to the area of the entire chip (the ratio is generally referred to as "overhead") is large. The test methods in which a test device is incorporated in a semiconductor device include not only the MBT method mentioned above but also an LMT (line mode test) method and an MMT (merged match test) method, but these methods also have such problems as mentioned above.